----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 20.02.2025 12:30:16
-- Design Name: 
-- Module Name: Brauns - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_logic_arith.all;
use Ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Brauns is
Port ( A: in std_logic_vector (7 downto 0) ;
B: in std_logic_vector (7 downto 0);
P: out std_logic_vector (15 downto 0));
--  Port ( );
end Brauns;

architecture behavioral of Brauns is

signal A1B0 : std_logic;
signal A2B0 : std_logic;
signal A3B0 : std_logic;
signal A4B0 : std_logic;
signal A5B0 : std_logic;
signal A6B0 : std_logic;
signal A7B0 : std_logic;
signal A0B1 : std_logic;
signal A1B1 : std_logic;
signal A2B1 : std_logic;
signal A3B1 : std_logic;
signal A4B1 : std_logic;
signal A5B1 : std_logic;
signal A6B1 : std_logic;
signal A7B1 : std_logic;
signal A0B2 : std_logic;
signal A1B2 : std_logic;
signal A2B2 : std_logic;
signal A3B2 : std_logic;
signal A4B2 : std_logic;
signal A5B2 : std_logic;
signal A6B2 : std_logic;
signal A7B2 : std_logic;
signal A0B3 : std_logic;
signal A1B3 : std_logic;
signal A2B3 : std_logic;
signal A3B3 : std_logic;
signal A4B3 : std_logic;
signal A5B3 : std_logic;
signal A6B3 : std_logic;
signal A7B3 : std_logic;
signal A0B4 : std_logic;
signal A1B4 : std_logic;
signal A2B4 : std_logic;
signal A3B4 : std_logic;
signal A4B4 : std_logic;
signal A5B4 : std_logic;
signal A6B4 : std_logic;
signal A7B4 : std_logic;
signal A0B5 : std_logic;
signal A1B5 : std_logic;
signal A2B5 : std_logic;
signal A3B5 : std_logic;
signal A4B5 : std_logic;
signal A5B5 : std_logic;
signal A6B5 : std_logic;
signal A7B5 : std_logic;
signal A0B6 : std_logic;
signal A1B6 : std_logic;
signal A2B6 : std_logic;
signal A3B6 : std_logic;
signal A4B6 : std_logic;
signal A5B6 : std_logic;
signal A6B6 : std_logic;
signal A7B6 : std_logic;
signal A0B7 : std_logic;
signal A1B7 : std_logic;
signal A2B7 : std_logic;
signal A3B7 : std_logic;
signal A4B7 : std_logic;
signal A5B7 : std_logic;
signal A6B7 : std_logic;
signal A7B7 : std_logic;


signal C1 : std_logic;  --P2
signal P2_1 : std_logic;  

signal C2 : std_logic; --p3
signal P3_1 : std_logic;
signal C8 : std_logic;
signal P3_2 : std_logic;

signal C3 : std_logic; --p4
signal P4_1 : std_logic;
signal C9 : std_logic;
signal P4_2 : std_logic;
signal C15 : std_logic;
signal P4_3 : std_logic;

signal C4 : std_logic;  --p5
signal P5_1 : std_logic;
signal C10 : std_logic;
signal P5_2 : std_logic;
signal C16 : std_logic;
signal P5_3 : std_logic;
signal C22 : std_logic;
signal P5_4 : std_logic;

signal C5 : std_logic;  --p6
signal P6_1 : std_logic;
signal C11 : std_logic;
signal P6_2 : std_logic;
signal C17 : std_logic;
signal P6_3 : std_logic;
signal C23 : std_logic;
signal P6_4 : std_logic;
signal C29 : std_logic;
signal P6_5 : std_logic;

signal C6 : std_logic;  --p7
signal P7_1 : std_logic;
signal C12 : std_logic;
signal P7_2 : std_logic;
signal C18 : std_logic;
signal P7_3 : std_logic;
signal C24 : std_logic;
signal P7_4 : std_logic;
signal C30 : std_logic;
signal P7_5 : std_logic;
signal C36 : std_logic;
signal P7_6 : std_logic;

signal C7 : std_logic;  --p8
signal P8_1 : std_logic;
signal C13 : std_logic;
signal P8_2 : std_logic;
signal C19 : std_logic;
signal P8_3 : std_logic;
signal C25 : std_logic;
signal P8_4 : std_logic;
signal C31 : std_logic;
signal P8_5 : std_logic;
signal C37 : std_logic;
signal P8_6 : std_logic;
signal C43 : std_logic;

signal C50 : std_logic;  --p9
signal P9_1 : std_logic;
signal C14 : std_logic;
signal P9_2 : std_logic;
signal C20 : std_logic;
signal P9_3 : std_logic;
signal C26 : std_logic;
signal P9_4 : std_logic;
signal C32 : std_logic;
signal P9_5 : std_logic;
signal C38 : std_logic;
--signal P9_6 : std_logic;
signal C44 : std_logic;

signal C51 : std_logic;  --p10
signal C21 : std_logic;
signal P10_1 : std_logic;
signal C27 : std_logic;
signal P10_4 : std_logic;
signal C33 : std_logic;
signal P10_5 : std_logic;
signal C39 : std_logic;
signal P10_6 : std_logic;
signal C45 : std_logic;

signal C52 : std_logic;  --p11
signal C28 : std_logic;
signal P11_4 : std_logic;
signal C34 : std_logic;
signal P11_5 : std_logic;
signal C40 : std_logic;
signal P11_6 : std_logic;
signal C46 : std_logic;

signal C53 : std_logic;  --p12
signal C35 : std_logic;
signal P12_1 : std_logic;
signal C41 : std_logic;
signal P12_6 : std_logic;
signal C47 : std_logic;

signal C54 : std_logic;  --p13
signal C42 : std_logic;
signal P13_1 : std_logic;
signal C48 : std_logic;

signal C55 : std_logic; --p14
signal C49 : std_logic;

signal C56 : std_logic; --P15



component Full_Addar is
Port ( A : in std_logic;
       B : in std_logic;
       Cin : in std_logic;
       S : out std_logic;
       Cout : out std_logic);
end component;

component Halfaddar is
port (A : in std_logic;
      B : in std_logic;
      S : out std_logic;
      Cout : out std_logic);
end component;


begin

A0B1 <= A(0) and B(1);
A0B2 <= A(0) and B(2);
A0B3 <= A(0) and B(3);
A0B4 <= A(0) and B(4);
A0B5 <= A(0) and B(5);
A0B6 <= A(0) and B(6);
A0B7 <= A(0) and B(7);
A1B0 <= A(1) and B(0);
A1B1 <= A(1) and B(1);
A1B2 <= A(1) and B(2);
A1B3 <= A(1) and B(3);
A1B4 <= A(1) and B(4);
A1B5 <= A(1) and B(5);
A1B6 <= A(1) and B(6);
A1B7 <= A(1) and B(7);
A2B0 <= A(2) and B(0);
A2B1 <= A(2) and B(1);
A2B2 <= A(2) and B(2);
A2B3 <= A(2) and B(3);
A2B4 <= A(2) and B(4);
A2B5 <= A(2) and B(5);
A2B6 <= A(2) and B(6);
A2B7 <= A(2) and B(7);
A3B0 <= A(3) and B(0);
A3B1 <= A(3) and B(1);
A3B2 <= A(3) and B(2);
A3B3 <= A(3) and B(3);
A3B4 <= A(3) and B(4);
A3B5 <= A(3) and B(5);
A3B6 <= A(3) and B(6);
A3B7 <= A(3) and B(7);
A4B0 <= A(4) and B(0);
A4B1 <= A(4) and B(1);
A4B2 <= A(4) and B(2);
A4B3 <= A(4) and B(3);
A4B4 <= A(4) and B(4);
A4B5 <= A(4) and B(5);
A4B6 <= A(4) and B(6);
A4B7 <= A(4) and B(7);
A5B0 <= A(5) and B(0);
A5B1 <= A(5) and B(1);
A5B2 <= A(5) and B(2);
A5B3 <= A(5) and B(3);
A5B4 <= A(5) and B(4);
A5B5 <= A(5) and B(5);
A5B6 <= A(5) and B(6);
A5B7 <= A(5) and B(7);
A6B0 <= A(6) and B(0);
A6B1 <= A(6) and B(1);
A6B2 <= A(6) and B(2);
A6B3 <= A(6) and B(3);
A6B4 <= A(6) and B(4);
A6B5 <= A(6) and B(5);
A6B6 <= A(6) and B(6);
A6B7 <= A(6) and B(7);
A7B0 <= A(7) and B(0);
A7B1 <= A(7) and B(1);
A7B2 <= A(7) and B(2);
A7B3 <= A(7) and B(3);
A7B4 <= A(7) and B(4);
A7B5 <= A(7) and B(5);
A7B6 <= A(7) and B(6);
A7B7 <= A(7) and B(7);



P0 : P(0) <= A(0) and B(0);

P1_0 : Halfaddar port map (A => A1B0, B=>A0B1, S=> P(1), Cout=>C1);

P21 : Full_Addar port map (A=>A2B0, B=>A1B1, Cin=>C1, S=>P2_1, Cout=>C2);
P2_0 : Halfaddar port map (A=>A0B2, B=>P2_1, S=>P(2), Cout=>C8);

P31 : Full_Addar port map (A=> A3B0, B=> A2B1, Cin=>C2, S=>P3_1, Cout=>C3);
P32 : Full_Addar port map (A=>A1B2, B=>P3_1 , Cin=>C8, S=>P3_2, Cout=>C9);
P3_0 : Halfaddar port map (A=>A0B3, B=>P3_2, S=>P(3), Cout=>C15);

P41 : Full_Addar port map (A=> A4B0, B=> A3B1, Cin=>C3, S=>P4_1, Cout=>C4);
P42 : Full_Addar port map (A=>A2B2, B=>P4_1 , Cin=>C9, S=>P4_2, Cout=>C10);
P43 : Full_Addar port map (A=>A1B3, B=>P4_2 , Cin=>C15, S=>P4_3, Cout=>C16);
P4_0 : Halfaddar port map (A=>A0B4, B=>P4_3, S=>P(4), Cout=>C22);

P51 : Full_Addar port map (A=> A5B0, B=> A4B1, Cin=>C4, S=>P5_1, Cout=>C5);
P52 : Full_Addar port map (A=>A3B2, B=>P5_1 , Cin=>C10, S=>P5_2, Cout=>C11);
P53 : Full_Addar port map (A=>A2B3, B=>P5_2 , Cin=>C16, S=>P5_3, Cout=>C17);
P54 : Full_Addar port map (A=>A1B4, B=>P5_3 , Cin=>C22, S=>P5_4, Cout=>C23);
P5_0 : Halfaddar port map (A=>A0B5, B=>P5_4, S=>P(5), Cout=>C29);

P61 : Full_Addar port map (A=> A6B0, B=> A5B1, Cin=>C5, S=>P6_1, Cout=>C6);
P62 : Full_Addar port map (A=>A4B2, B=>P6_1 , Cin=>C11, S=>P6_2, Cout=>C12);
P63 : Full_Addar port map (A=>A3B3, B=>P6_2 , Cin=>C17, S=>P6_3, Cout=>C18);
P64 : Full_Addar port map (A=>A2B4, B=>P6_3 , Cin=>C23, S=>P6_4, Cout=>C24);
P65 : Full_Addar port map (A=>A1B5, B=>P6_4 , Cin=>C29, S=>P6_5, Cout=>C30);
P6_0 : Halfaddar port map (A=>A0B6, B=>P6_5, S=>P(6), Cout=>C36);

P71 : Full_Addar port map (A=> A7B0, B=> A6B1, Cin=>C6, S=>P7_1, Cout=>C7);
P72 : Full_Addar port map (A=>A5B2, B=>P7_1 , Cin=>C12, S=>P7_2, Cout=>C13);
P73 : Full_Addar port map (A=>A4B3, B=>P7_2 , Cin=>C18, S=>P7_3, Cout=>C19);
P74 : Full_Addar port map (A=>A3B4, B=>P7_3 , Cin=>C24, S=>P7_4, Cout=>C25);
P75 : Full_Addar port map (A=>A2B5, B=>P7_4 , Cin=>C30, S=>P7_5, Cout=>C31);
P76 : Full_Addar port map (A=>A1B6, B=>P7_5 , Cin=>C36, S=>P7_6, Cout=>C37);
P7_0 : Halfaddar port map (A=>A0B7, B=>P7_6, S=>P(7), Cout=>C43);

P81 : Halfaddar port map (A=>A7B1, B=>C7, S=>P8_1, Cout=>C50);
P82 : Full_Addar port map (A=>A6B2, B=>P8_1 , Cin=>C13, S=>P8_2, Cout=>C14);
P83 : Full_Addar port map (A=>A5B3, B=>P8_2 , Cin=>C19, S=>P8_3, Cout=>C20);
P84 : Full_Addar port map (A=>A4B4, B=>P8_3 , Cin=>C25, S=>P8_4, Cout=>C26);
P85 : Full_Addar port map (A=>A3B5, B=>P8_4 , Cin=>C31, S=>P8_5, Cout=>C32);
P86 : Full_Addar port map (A=>A2B6, B=>P8_5 , Cin=>C37, S=>P8_6, Cout=>C38);
P8_0: Full_Addar port map (A=>A1B7, B=>P8_6 , Cin=>C43, S=>P(8), Cout=>C44);

P91 : Full_Addar port map (A=>A7B2, B=>C50 , Cin=>C14, S=>P9_1, Cout=>C51);
P92 : Full_Addar port map (A=>A6B3, B=>P9_1 , Cin=>C20, S=>P9_2, Cout=>C21);
P93 : Full_Addar port map (A=>A5B4, B=>P9_2 , Cin=>C26, S=>P9_3, Cout=>C27);
P94 : Full_Addar port map (A=>A4B5, B=>P9_3 , Cin=>C32, S=>P9_4, Cout=>C33);
P95 : Full_Addar port map (A=>A3B6, B=>P9_4 , Cin=>C38, S=>P9_5, Cout=>C39);
P9_0 : Full_Addar port map (A=>A2B7, B=>P9_5 , Cin=>C44, S=>P(9), Cout=>C45);

P101 : Full_Addar port map (A=>A7B3, B=>C51 , Cin=>C21, S=>P10_1, Cout=>C52);
P102 : Full_Addar port map (A=>A6B4, B=>P10_1 , Cin=>C27, S=>P10_4, Cout=>C28);
P103 : Full_Addar port map (A=>A5B5, B=>P10_4 , Cin=>C33, S=>P10_5, Cout=>C34);
P104 : Full_Addar port map (A=>A4B6, B=>P10_5 , Cin=>C39, S=>P10_6, Cout=>C40);
P10_0 : Full_Addar port map (A=>A3B7, B=>P10_6 , Cin=>C45, S=>P(10), Cout=>C46);

P111 : Full_Addar port map (A=>A7B4, B=>C52 , Cin=>C28, S=>P11_4, Cout=>C53);
P112 : Full_Addar port map (A=>A6B5, B=>P11_4 , Cin=>C34, S=>P11_5, Cout=>C35);
P113 : Full_Addar port map (A=>A5B6, B=>P11_5 , Cin=>C40, S=>P11_6, Cout=>C41);
P11_0 : Full_Addar port map (A=>A4B7, B=>P11_6 , Cin=>C46, S=>P(11), Cout=>C47);

P121 : Full_Addar port map (A=>A7B5, B=>C53 , Cin=>C35, S=>P12_1, Cout=>C54);
P122 : Full_Addar port map (A=>A6B6, B=>P12_1 , Cin=>C41, S=>P12_6, Cout=>C42);
P12_0 : Full_Addar port map (A=>A5B7, B=>P12_6 , Cin=>C47, S=>P(12), Cout=>C48);

P131 : Full_Addar port map (A=>A7B6, B=>C54 , Cin=>C42, S=>P13_1, Cout=>C55);
P13_0 : Full_Addar port map (A=>A6B7, B=>P13_1 , Cin=>C48, S=>P(13), Cout=>C49);

P14_0 : Full_Addar port map (A=>A7B7, B=>C55 , Cin=>C49, S=>P(14), Cout=>C56);

P15_0 : P(15) <= C56;


end Behavioral;
